1. Technical Field
The present disclosure relates to a gate driving circuit, and more particularly, to a gate driving circuit including a shift register and a display device including the gate driving circuit.
2. Discussion of the Related Art
Recently, as the information society progresses, display devices processing and displaying a large amount of information have rapidly advanced and various flat panel displays (FPDs) have been developed. For example, the FPDs may include liquid crystal display (LCD) devices, plasma display panel (PDP) devices, organic light emitting diode (OLED) display devices and field emission display (FED) devices.
In general, a display device includes a display panel displaying an image and a driving unit supplying a signal and a power to the display panel. The driving unit includes a gate driving unit and a data driving unit supplying a gate voltage and a data voltage, respectively, to a pixel region of the display panel.
The driving unit may be formed as a printed circuit board (PCB), and PCBs for the gate driving unit and the data driving unit are attached to a pad region at the periphery of the display panel. However, when the PCBs for the gate driving unit and the data driving unit are attached to a pad region of the display panel, a volume and a weight of the display device increase.
Accordingly, a gate-in-panel (GIP) type display device where a part of the gate driving unit such as a shift register is formed on an array substrate of the display panel and a single PCB including the other part of the gate driving unit and the data driving unit is attached to the display panel has been suggested.
The GIP type display device will be illustrated referring to drawings.
FIG. 1 is a view showing a stage of a shift register of a gate-in-panel type display device according to the related art, and FIG. 2 is a timing chart showing a plurality of signals for a shift register of a gate-in-panel type display device according to the related art.
In FIGS. 1 and 2, a shift register of a gate-in-panel (GIP) type display device according to the related art includes a plurality of stages SRS and generates a gate voltage VG supplied to a display panel using a high level power voltage VDD, a low level power voltage VSS, a start voltage VST, a next stage gate voltage VNEXT and a clock CLK. Each stage SRS of the shift register includes first to ninth thin film transistors (TFTs) T1 to T9.
The gate voltage VG is outputted from a node between a source of the eighth TFT T8 and a drain of the ninth TFT T9. The clock CLK is applied to a drain of the eighth TFT T8, and the low level power voltage VSS is applied to a source of the ninth TFT T9. Accordingly, the clock CLK is outputted as the gate voltage VG while the eighth TFT T8 is turned on, and the low level power voltage VSS is outputted as the gate voltage VG while the ninth TFT T9 is turned on.
Voltages of gates of the eighth and ninth TFTs T8 and T9 are determined by first to seventh TFTs T1 to T7 and the start voltage VST. During a first time section TS1, since a high level voltage is applied to a Q node and the gate of the eighth TFT T8 to turn on the eighth TFT T8, a low level voltage of the clock CLK is outputted as the gate voltage VG. During a second time section TS2, since a high level voltage of the clock CLK is applied to the drain of the eighth TFT T8 and the high level voltage of the gate of the eighth TFT T8 becomes a higher level voltage by boosting to turn on the eighth TFT T8, the high level voltage of the clock CLK is outputted as the gate voltage VG.
During a third time section TS3, since a high level voltage is applied to the Q node and the gate of the eighth TFT T8 to turn on the eighth TFT T8, the low level voltage of the clock CLK is outputted as the gate voltage VG. During the first to third time sections TS1 to TS3, a low level voltage is applied to a QB node and gates of the third and ninth TFTs T3 and T9, and the third and ninth TFTs T3 and T9 maintain a turn-off state.
During a fourth time section TS4, since a low level voltage is applied to the Q node and the gate of the eighth TFT T8 to turn off the eighth TFT T8 and a high level voltage is applied to the QB node and the gates of the third and ninth TFTs T3 and T9 to turn on the third and ninth TFTs T3 and T9, the low level power voltage VSS is outputted as the gate voltage VG.
In each stage of the shift register according to the related art, the eighth TFT T8 is turned on during the first to third time sections TS1 to TS3 corresponding to three horizontal periods 3H of one frame 1F and is turned off during the other fourth time section T4, while the third and ninth TFTs T1 and T9 are turned off during the first to third time sections TS1 to TS3 corresponding to three horizontal periods 3H of one frame 1F and are turned on during the other fourth time section T4.
Accordingly, the shift register may not normally operate due to deterioration of the third and ninth TFTs T3 and T9. To solve the above problems, a method of improving reliability by dividing a turn-on time of the ninth TFT T9 has been suggested. However, since the above method has a limit that a turn-on time of the ninth TFT T9 does not absolutely decrease, the above method is not applied to a display device requiring high reliability.